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| White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL* 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA FEATURES Double-data-rate architecture DDR266, DDR333, and DDR400 Bi-directional data strobes (DQS) Phase-lock loop (PLL) clock driver to reduce loading Differential clock inputs (CK & CK#) ECC error detection and correction Programmable Read Latency 2, 2.5 (clock) Programmable Burst Length (2, 4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank RoHS compliant products Power Supply: * VCC = VCCQ = +2.5V 0.2 (133 and 166MHz) * VCC = VCCQ = +2.6V 0.1 (200MHz) JEDEC standard 184 pin DIMM package * Package height options: Low-profile: 30.48mm (1.20") MAX NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option * This product is subject to change without notice. DESCRIPTION The W3EG2128M72AFSR is a 2x128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of thirtysix 128Mx4 components, in FBGA packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR400@CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DDR333@CL=2.5 166MHz 2.5-3-3 DDR266@CL=2 133MHz 2-2-2 DDR266@CL=2 133MHz 2-3-3 DDR266@CL=2.5 133MHz 2.5-3-3 January 2006 Rev. 3 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VCC NC NC VSS DQ10 DQ11 CKE0 VCC DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCC DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCC DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCC WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS NC NC VCC DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCC DQS9 DQ6 DQ7 VSS NC NC NC VCC DQ12 DQ13 DQS10 VCC DQ14 DQ15 CKE1 VCC NC DQ20 A12 VSS DQ21 A11 DQS11 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCC DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VCC CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS DQS17 A10 CB6 VCC CB7 VSS DQ36 DQ37 VCC DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCC CS0# CS1# DQS14 VSS DQ46 DQ47 NC VCC DQ52 DQ53 NC VCC DQS15 DQ54 DQ55 VCC NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VCC SA0 SA1 SA2 VCCSPD W3EG2128M72AFSR-D3 -AD3 FINAL PIN NAMES A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS17 CK0 CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VCC VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC RESET# Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Power Supply Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect Reset Enable January 2006 Rev. 3 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL FUNCTIONAL BLOCK DIAGRAM VSS RCS1# RCS0# DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS9 DQ4 DQ5 DQ6 DQ7 DQS10 DQ12 DQ1 DQ13 DQ14 DQ15 DQS11 DQ20 DQ21 DQ2 DQ22 DQ23 DQS12 DQ28 DQ29 DQ30 DQ31 DQS13 DQ36 DQ37 DQ38 DQ39 DQS14 DQ44 DQ45 DQ46 DQ47 DQS15 DQ52 DQ53 DQ54 DQ55 DQS16 DQ60 DQ61 DQ62 DQ63 DQS17 CB4 CB5 CB6 CB7 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS# DM CS0# CS1# BA0,BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# R E G I S T E R RCS0# RCS1# RBA0,RBA1 RA0-RA12 RRAS# RCAS# RCKE0 RCKE1 RWE# CK0 PLL BA0,BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE: DDR SDRAMs CKE: DDR SDRAMs WE#: DDR SDRAMs SDRAM REGISTER VCCSPD VCC/VCC Q SPD/EEPROM DDR SDRAM CK0# SERIAL PD SCL WP SDA A0 SA0 A1 SA1 A2 SA2 VREF VSS DDR SDRAM DDR SDRAM PCK PCK# RESET# NOTE: All resistor values are 22 unless otherwise specified. NOTES: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. January 2006 Rev. 3 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD I0S Value -0.5 - 3.6 -1.0 - 3.6 -55 - +150 27 50 Units V V C W mA Note: * Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. * Functional operation should be restricted to recommended operating condition. * Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS 0C TA 70C, VCC = 2.5V 0.2V Parameter Supply Voltage* Supply Voltage* Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Current Output Low Current Note: Symbol VCC VCCQ VREF VTT VIH VIL IOH IOL Min 2.3 2.3 .49 x VCCQ VREF - .04 VREF + 0.15 -0.3 16.8 16.8 Max 2.7 2.7 .51 x VCCQ VREF + .04 VCCQ + 0.3 VREF - 0.15 -- -- Unit V V V V V V mA mA * DDR400 VCC = VCCQ = 2.6V 0.1V. CAPACITANCE TA = 25C, f = 1MHz, VCC = 2.5V 0.2V Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CK0, CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT Max 5.5 5.5 5.5 5.5 5.5 13.0 5.5 13.0 13.0 Unit pF pF pF pF pF pF pF pF pF Note: * These parameters serve to support both SAMSUNG and MICRON components based modules. January 2006 Rev. 3 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL Recommended operating conditions, 0C TA +70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V. Includes DDR SDRAM components only Rank 1 Conditions One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low) CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE = (low) CS# = High; CKE = High; One device bank; ActivePrecharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. DDR400@CL=3 Max 3870 DDR333@CL=2.5 Max 2780 DDR266@CL=2, 2.5 Max 2790 Rank 2 Standby State ICC3N ICC SPECIFICATIONS AND TEST CONDITIONS Parameter Operating Current Symbol ICC0 Units mA Operating Current ICC1 4410 3780 3780 mA ICC3N Precharge PowerDown Standby Current Idle Standby Current ICC2P 180 180 180 rnA ICC2P ICC2F 1980 1620 1620 mA ICC2F Active Power-Down Standby Current Active Standby Current ICC3P ICC3N 1620 2160 1260 1800 1260 1800 mA mA ICC3P ICC3N Operating Current ICC4R 4500 3870 3870 mA ICC3N Operating Current ICC4W 4590 4050 3690 rnA ICC3N Auto Refresh Current Self Refresh Current Operating Current ICC5 ICC6 ICC 7A 7290 180 9180 6120 180 8190 6120 180 8100 mA mA mA ICC3N ICC6 ICC3N Note: * These parameters serve to support both SAMSUNG and MICRON components based modules. January 2006 Rev. 3 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL DETAILED TEST CONDITIONS FOR DDR SDRAM ICC1 & ICC7A ICC1 : OPERATING CURRENT : ONE BANK 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRCD=15*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst * ICC7A : OPERATING CURRENT : FOUR BANKS 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst 4. 4. * * * * * * * Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 January 2006 Rev. 3 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS DDR400: VCC = VCCQ = +2.6V 0.1V; DDR333, 266: VCC = VCCQ = +2.5V 0.2V AC Characteristics Parameter Access window of DQs from CK, CK# CK high-level width CK low-level width Clock cycle time CL=3 CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK, CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK, CK# Data-out low-impedance window from CK, CK# Address and control input hold time (slew rate >/ =.5V/ns) Address and control input set-up time (slew rate >/ =.5V/ns) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command Symbol tAC tCH tCL tCK (3) tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHf tISf tIHs tISs tIPW tMRD tQH tQHS tRAS tRAP 40 15 -0.70 0.60 0.60 N/A N/A 2.2 10 tHP-tQHS 0.55 70,000 42 15 0.72 0.2 0.2 tCH, tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 tHP-tQHS 0.55 70,000 40 15 Min -0.70 0.45 0.45 5 6 7.5 0.40 0.40 1.75 -0.60 0.35 0.35 0.40 1.28 0.75 0.2 0.2 tCH, tCL +0.70 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 40 15 +0.60 403 Max +0.70 0.55 0.55 7.5 12 12 Min -0.70 0.45 0.45 6 6 7.5 0.45 0.45 1.75 -0.60 +0.60 0.35 0.35 0.45 1.25 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 335 Max +0.70 0.55 0.55 13 12 12 Min -0.75 0.45 0.45 7.5 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.75 262 Max +0.75 0.55 0.55 13 12 12 Min -0.75 0.45 0.45 7.5 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 +0.75 265 Max +0.75 0.55 0.55 13 12 12 Units ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns 15 13,14 18 8,19 8,20 6 6 6 6 13,14 16 16 22 22 22 14,17 14,17 17 Notes Note: * These parameters serve to support both SAMSUNG and MICRON components based modules. Continued on next page January 2006 Rev. 3 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) DDR400: VCC = VCCQ = +2.6V 0.1V; DDR333, 266: VCC = VCCQ = +2.5V 0.2V AC Characteristics Parameter ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VCC Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Symbol tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFI tVTD tXSNR tXSRD 0 70 200 Min 55 70 15 15 0.9 0.4 10 0.25 0 0.4 15 2 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 403 Max Min 60 72 15 15 0.9 0.4 12 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 335 Max Min 60 75 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 262 Max Min 60 75 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0.6 1.1 0.6 265 Max Units ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK 13 12 12 10,11 9 21 Notes Note: * These parameters serve to support both SAMSUNG and MICRON components based modules. January 2006 Rev. 3 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Notes 1. 2. All voltages referenced to VSS Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. Outputs are measured with equivalent load: 12. 11. W3EG2128M72AFSR-D3 -AD3 FINAL It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: x4 = DQS with DQ0-DQ3. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 3. VTT TT 50 Reference Point 30pF 13. Output (VOUT (VOUT) 4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). For slew rates less than 1V/ns and greater than or equal to 0.5V/ ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 335, slew rates must be greater than or equal to 0.5V/ns. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VCCQ is recognized as LOW. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). The intent of the "Don't Care" state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 14. 15. 5. 16. 17. 6. 18. 19. 7. 8. 20. 21. 9. 22. 10. January 2006 Rev. 3 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Part Number W3EG2128M72AFSR265D3xG Speed/Data Rate 133MHz/266Mb/s 2.5 W3EG2128M72AFSR-D3 -AD3 FINAL tRCD 3 tRP 3 Height* 30.48 (1.20") MAX ORDERING INFORMATION FOR D3 CAS Latency NOTES: * RoHS compliant product. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option * In an effort to support our customer's traceability and control requirements (which enables them to quickly identify component speed grades used on modules in the field); WEDC has created a "26A" module part number option. The W3EG2128M72AFSR26AD3xG product part number meets all the requirements of the W3EG2128M72AFSR265D3xG product however it is built using 400Mhz rated components. We recommend therefore that customers include both the "26A" and "265" final part numbers on their AVL in order to support flexibility of sourcing and to allow for the best module sourcing lead times. For those customers who wish to allow both sourcing options but only would like to include one product part number on their AVL, WEDC can accommodate. Please consult factory for more details. LOW-PROFILE D3 184-PIN DDR DIMM DIMENSIONS FRONT VIEW 133.20 (5.255) 3.81 (0.150) (0.150 MAX 2.00 (0.079) R (4x) 30.48 (1.2) MAX 17.78 (0.700) TYP. 2.50 (0.098) D (2X) 2.30 (0.091) TYP. PIN 1 2.30 (0.091) TYP. 1.27 (0.050) 1.02 (0.040) TYP. TYP. 64.77 (2.55) 0.90 (0.035) R 90 6.35 (0.250) TYP. 50) 49.53 (1.95) 120.65 (4.750) (4.75 10.00 (0.394) TYP. 1.37 (0.054) PIN 92 BA BACK VIEW PIN 184 PIN 93 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). January 2006 Rev. 3 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL ORDERING INFORMATION FOR AD3 Part Number W3EG2128M72AFSR403AD3XG W3EG2128M72AFSR335AD3xG W3EG2128M72AFSR262AD3xG W3EG2128M72AFSR263AD3xG W3EG2128M72AFSR265AD3xG Speed/Data Rate 200MHz/400Mb/s 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 133MHz/266Mb/s CAS Latency 3 2.5 2 2 2.5 tRCD 3 3 2 3 3 tRP 3 3 2 3 3 Height* 30.48 (1.20") MAX 30.48 (1.20") MAX 30.48 (1.20") MAX 30.48 (1.20") MAX 30.48 (1.20") MAX NOTES: * RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option * In an effort to support our customer's traceability and control requirements (which enables them to quickly identify component speed grades used on modules in the field); WEDC has created a "26A" module part number option. The W3EG2128M72AFSR26AAD3xG product part number meets all the requirements of the W3EG2128M72AFSR265AD3xG product however it is built using 400Mhz rated components. We recommend therefore that customers include both the "26A" and "265" final part numbers on their AVL in order to support flexibility of sourcing and to allow for the best module sourcing lead times. For those customers who wish to allow both sourcing options but only would like to include one product part number on their AVL, WEDC can accommodate. Please consult factory for more details. LOW-PROFILE AD3 184-PIN DDR DIMM DIMENSIONS FRONT VIEW 133.20 (5.255) 3.81 (0.150) MAX 2.00 (0.079) R (4x) 30.48 (1.2) MAX 17.78 (0.700) TYP. 2.50 (0.098) D (2X) 2.30 (0.091) TYP. PIN 1 2.30 (0.091) TYP. 1.27 (0.050) 1.02 (0.040) TYP. TYP. 64.77 (2.55) 0.90 (0.035) R 6.35 (0.250) TYP. 49.53 (1.95) 120.65 (4.750) 10.00 (0.394) TYP. 1.37 (0.054) PIN 92 BACK VIEW PIN 184 PIN 93 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). January 2006 Rev. 3 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL PART NUMBERING GUIDE W 3 E G 2 128M 72 A F S R xxx A D3 x G WEDC MEMORY (SDRAM) DDR GOLD DUAL RANKS DEPTH BUS WIDTH COMPONENT WIDTH x4 FBGA 2.5V REGISTERED SPEED/DATA RATE (Mb/s) NEW REVISION (184 Pin) PACKAGE COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT January 2006 Rev. 3 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title W3EG2128M72AFSR-D3 -AD3 FINAL 2GB - 2x128Mx72, DDR SDRAM Registered ECC, w/PLL, FBGA Revision History Rev # Rev 0 Rev 1 History Initial Release 1.1 Added Lead-free option 1.2 Added vendor code options M = Micron S = Samsung Release Date September 2004 November 2004 Status Advanced Advanced Rev 2 2.1 Removed DDR200 specifications 2.2 Added "AD3" package option 2.3 Added the "26A" module part number option 2.4 Indicated "D3" not recommanded for new design or new qualifications, insted use "AD3" option 2.5 Removed 333Mb/s, 266Mb/s (CL 2-2-2), 266Mb/s (CL 2-3-3) and 200Mb/s (CL 2-2-2) specifications for "D3" package option 2.6 Added "A" in part number guide. December 2005 Advanced Rev 3 3.1 Added 400 MHz clock speed 3.2 Datasheet AC's and DC's updated to support both Micron's 512Mb specification: 512MBDDRx4x8x16_1.fm-revJ1/06EN and Samsung's 512Mb C-Die specification: Rev 1.1 June 2005 3.3 Data Sheet move to final January 2006 Final January 2006 Rev. 3 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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